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Patterns of Ladder Logic Programming

If you’re familiar with PC programming in languages like Java or C#, then you’ll probably know about the books Design Patterns: Elements of Reusable Object-Oriented Software and Patterns of Enterprise Application Architecture. These books are about Software Design Patterns.

As a long time ladder logic programmer, I thought one way to share my experience with newer programmers is to organize a list of common patterns used in ladder logic programming. This list of ladder logic programming patterns serves two purposes: first, each pattern is a tool for solving a common problem using ladder logic, and having these patterns in your toolbox will allow you to program faster and spend more time focusing on the higher level structure of your program. Second, since these are common patterns, you’ll start to find it easier to read other people’s ladder logic, and other experienced programmers will find it easier to follow your logic.

  1. The Sealed in Coil pattern
  2. The State Coil/Fault Coil pattern
  3. The Start/Stop Circuit pattern
  4. The Set/Reset pattern
  5. The Flasher pattern
  6. The Debounce pattern
  7. The Input Map pattern
  8. The Step pattern
  9. The Mission pattern
  10. The Five Rung pattern
  11. The Mode pattern

8 comments

  • eplc · November 13, 2015 at 9:26 am

    I do think this is a great idea. Keep posting!

  • codezs09 · February 6, 2016 at 12:58 pm

    Very useful. Thank you for sharing

  • Cheng · February 15, 2016 at 10:29 am

    Very useful and detailed

  • LKH · March 8, 2016 at 8:29 am

    Very nice idea for people just starting out!
    You should include an Anti-Tie Down pattern 🙂

  • Bob · June 24, 2016 at 3:45 pm

    Very nice. I hope you keep adding new sections to this. Naming conventions, Fault – Acknowledgement pattern, Messages/Warnings/Alarms ect.

    I will be sharing this with my colleagues.

  • narakirin · November 28, 2016 at 1:43 am

    Thank you very much

  • azetou · November 8, 2017 at 2:18 am

    Thank you sir for your efforts. Just one question, when you show the timing diagram shouldn’t we see the clock in it? it means you have to add at what intervals the CPU updates the inputs and outputs. Thanks for clearing this up for me.

  • Author comment by Scott Whitlock · November 8, 2017 at 10:24 am

    @azetou – A clock signal would make sense for combinational logic with internally clocked registers, but a PLC is just simulating combinational logic with a sequential program. In a TTL circuit, the clock causes the registers (flip-flops) to update their outputs, which then changes the downstream logic from those elements. In a PLC, every instruction potentially causes the update of internal state, but the logic that depends on that state change doesn’t actually change until those instructions execute. Example if you have two rungs: A := A + 1, and the second rung is A := A – 1, then during the scan A both increments and decrements. A program with 100 rungs could have potentially hundreds or even thousands of “clock pulses” every scan.

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